The present disclosure relates to a multilayer ceramic capacitor and a board having the same.
In accordance with the recent trend for the miniaturization and increases in the capacitance of electronic products, demands have increasingly been made for electronic components used in electronic products to be relatively small while having high capacitance.
Among electronic components, in the case of multilayer ceramic capacitors, when equivalent series inductance (hereinafter, referred to as “ESL”) increases, performance of electronic products in which the capacitors are provided may be deteriorated. In addition, in accordance with the miniaturization of the electronic products and increases in the capacitance of the electronic components, increases in ESL of the multilayer ceramic capacitors may have a relatively significant effect on deteriorations in performance of the electronic products.
Particularly, in accordance with increases in the performance of integrated circuits (IC), decoupling capacitors have been increasingly used therein. Therefore, demand for multilayer ceramic capacitors (MLCCs) having a 3-terminal vertical multilayer structure, so-called “low inductance chip capacitors (LICC)”, capable of decreasing inductance in capacitors by decreasing a distance between external terminals to decrease a current flow path, has increased.
In the case of such multilayer ceramic capacitors, reliability and mounting defect rates may be significantly affected by the shapes and sizes of external electrodes.